Contemporary computer systems implement virtual memory systems in order to create the illusion of a very large amount of memory that is exclusively available for each application run on a system. Typically, a specific amount of virtual memory is made available to each application, with each application being provided a separate space identifier that is used to separate memory associated with a particular application from others. The virtual memory is mapped to physical memory.
Mapping from a virtual address to a physical address is handled by a translation lookaside buffer (TLB). The TLB is a cache within a microprocessor that provides translations in the form of page table entries. The translations are typically generated using data structures in memory called “page tables”, using an algorithm implemented in hardware or software. The results of executing this algorithm are stored in the TLB for future use. In conventional TLB pipelines, an effective address must be generated before the TLB can be indexed for a translation. However, having to wait for an address to be generated results in longer translation times.